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X28HC256
Page Write Operation
The page write feature of the X28HC256 allows the entire
memory to be written in typically 0.8 seconds. Page write
allows up to one hundred twenty-eight bytes of data to be
consecutively written to the X28HC256, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A 7 through A 14 ) for each subsequent valid
write cycle to the part during this operation must be the same
as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100μs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition
is not detected within 100μs, the internal automatic
programming cycle will commence. There is no page write
window limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 100μs.
Write Operation Status Bits
The X28HC256 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
cease, and the device will be accessible for additional read
and write operations.
DATA Polling I/O
DATA Polling can effectively halve the time for writing to the
X28HC256. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
The Toggle Bit I/O
The Toggle Bit can eliminate the chore of saving and fetching
the last address and data in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC256 memories that is frequently updated.
The timing diagram in Figure 4 illustrates the sequence of
events on the bus. The software flow diagram in Figure 5
illustrates a method for polling the Toggle Bit.
Hardware Data Protection
The X28HC256 provides two hardware features that protect
nonvolatile data from inadvertent writes.
? Default V CC Sense—All write functions are inhibited when
V CC is 3.5V typically.
Write Inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during power-up
and power-down, maintaining data integrity.
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O 7 )
The X28HC256 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC256. This eliminates
additional interrupt inputs or external hardware. During the
internal programming cycle, any attempt to read the last byte
written will produce the complement of that data on I/O 7 (i.e.,
write data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O 7 will reflect true data.
Toggle Bit (I/O 6 )
The X28HC256 also provides another method for
determining when the internal write cycle is complete. During
the internal programming cycle I/O 6 will toggle from HIGH to
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete the toggling will
4
FN8108.3
September 21, 2011
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